//
// Created by 32827 on 2024/7/24.
//

#ifndef STM32FPGAR_YZL_NONE_AD9850_H
#define STM32FPGAR_YZL_NONE_AD9850_H
#include "yzl.h"

#define YZL_AD9850_CTRL_CONTROL_POS 0x0
#define YZL_AD9850_CTRL_CONTROL (0b11<<YZL_AD9850_CTRL_CONTROL_POS)

#define YZL_AD9850_CTRL_POWER_DOWN_POS 0x2
#define YZL_AD9850_CTRL_POWER_DOWN (0b1<<YZL_AD9850_CTRL_POWER_DOWN_POS)

#define YZL_AD9850_CTRL_PHASE_POS 0x03
#define YZL_AD9850_CTRL_PHASE (0b11111<<YZL_AD9850_CTRL_PHASE_POS)

typedef struct {
    YZL_GPIO W_CLK;
    YZL_GPIO FQ_Update;
    YZL_GPIO DATA_OUT;
    YZL_GPIO RESET;
    uint8_t control;
    uint32_t frequency;
} YZL_AD9850_DEF;

YZF_RESULT yzl_ad9850_init(YZL_AD9850_DEF *ad9850);
YZF_RESULT yzl_ad9850_set_power_down(YZL_AD9850_DEF *ad9850,YZF_BOOL isDown);
YZF_RESULT yzl_ad9850_set_phase(YZL_AD9850_DEF *ad9850,uint8_t phase);
YZF_RESULT yzl_ad9850_set_frequency(YZL_AD9850_DEF *ad9850,uint32_t frequency);
YZF_RESULT yzl_ad9850_fresh(YZL_AD9850_DEF *ad9850);
YZF_RESULT yzl_ad9850_reset(YZL_AD9850_DEF *ad9850);
#endif //STM32FPGAR_YZL_NONE_AD9850_H
